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powerful energy meter chipset adsst-salem-3t rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures high accu racy supports iec 60687/610 36 an d a n si c12. 1/12.20 suitable for cla ss0.5 and class 0 .2 meter full four quadr a nt measur em ent of paramet e rs spi? compatibl e serial interfac e pulse outp ut w i th programmable pulse const a nt as pulses/kwh or wh/pulse programmable dut y cycle for pulse output embedded cali bration routines for gain and dc offset software based phase an d nonlinearity com p ensation for current transformers 15 kh z samplin g frequency uart mode en ables a p c to di rectly access al l computed parameters flags to indicat e tamper conditions single 3.0 v su pply deve lopers kit to accelerate design process (see ordering gui d e for separate ordering num b er.) general description the a d sst - s a lem-3t e n erg y m e ter chi p s e t c o n s ists o f a n ef f i cien t adss t - 218x dig i t a l sig n al p r o c es s o r (ds p ), a fast an d acc u ra t e 6-cha n n e l , 16-b i t ads s t - 73360l ar s i g m a-de l t a a n a - l o g - to - d i g it a l c o n v e r te r ( a d c ) , and me te r i ng s o f t w a re. t w o chi p s e t v e rsio n s a r e a v a i la b l e t o s u p p o r t dif f er ing ra n g es o f o p era t in g t e m p era t ur e: the adss t - em-3040 chi p s e t is r a t e d a t 0c t o 70c f o r co mm er cial a p plica t ion s , while t h e ads s t - em- 3041 c h i p s e t o p era t es a t C25c t o +85c f o r ind u s t r i al us e . c dsp buttons ct smps lcd display rtc flash spi bus rs-232 opto ct ct adc adsst-em-3040 resistor block boot flash 03 738 - 0 - 0 0 1 f i g u re 1. b l o c k d i a g r a m of a f u nc t i on al m e te r the a d c and ds p a r e i n t e r f ace d t o si m u l t ane o us l y acq u ir e v o l t a g e and c u r r en t s a m p les o n al l t h r e e phas es a nd t o p e r f o r m ma t h em a t ica l ly in t e n s i v e com p u t a t ion s t o ca lc u l a t e va r i o u s in st an t a ne o u s p a ra m e t e rs an d p e r f o r m ha r m o n ic a n a l y s is. th e ch i p s e t c a n b e i n te r f a c e d to a n y ge ne r a l - pu r p o s e mi c r opro c e s- s o r to d e vel op s t a t e of t h e ar t t r i - ve c t or or p o ly ph a s e e n e r g y me te r i ng s o lut i ons w i t h a w i d e r a nge of b a s i c c u r r e n t s f r om 1 a t o 30 a. b y in cor p o r a t in g a com p r e h e n s i v e da ta s e t o f p a ra m e - t e rs, in cl ud in g i n st an t a n e o u s me asur emen t s , ac c u m u la t e d p a r a me t e rs , an d h a r m on i c an a l y s i s d a t a , t h e a d s s t - s a l e m - 3 t chi p s e t m e ets hi g h e n d e n erg y m e t e r i n g r e q u irem e n ts. the a b i l - i t y t o e a si l y co nf igur e t h e chi p s e t fo r va r i o u s p a ra m e ters ma k e s i t a v e r y f l exi b le s o l u tio n . the phas e an d n o nl ine a r i ty com p e n s a t i on fo r c u r r en t t r a n sfo r m e rs is do ne in s o f t w a r e (p a t en t p e ndi n g ) w i t h ou t ha vin g t o us e an y p a s s i v e co m p o n e n ts in t h e ci r c ui t fo r c o m p e n s a ti o n , th u s m i n i m i z i n g v a ri a t i o n s i n a ccu r a c y w i t h t e m p era t ur e and t i m e . the a d sst - s a lem-3t m e as u r es a n d co m p u t es a la rg e n u m - ber o f p a ra m e t e r s es sen t ial f o r high en d m e t e r i n g . table 1. p a r a m e t e r e a c h p h a s e t o t a l rms voltage rms current active power apparent power inductive reacti ve power capacitive reac tive power power factor frequency positive active energy negative active energy apparent energ y positive inductive reactive energy negative inductive reactive ene r gy positive capa citive reactive ene r gy negative capaci tive reactive energy voltage magnitude and phase for all odd harmonics up to 21 st order current magnit ude and phase for all odd harmonics up to 21 st order the a d sst - s a lem-3t o f fers s o me exce l l en t fe a t ur es t h a t m a k e t h e fi n a l m e t e r c o s t - e ff e c t i v e a n d ea s y t o m a n u f a ct u r e .
adsst-salem-3t rev. 0 | page 2 of 24 table of contents easy calibration ............................................................................ 3 effective phase compensation ................................................... 3 ease of design ............................................................................... 3 quadrant and other conventions ............................................. 3 general description of the adsst-218x dsp ......................... 4 architecture overview ................................................................ 4 adsst-218x common-mode pins ........................................... 6 clock signals ................................................................................. 7 reset ............................................................................................ 7 recommended operating conditions ...................................... 7 adsst-218x electrical characteristics ......................................... 8 absolute maximum ratingsadsst-218x ................................. 9 esd caution .................................................................................. 9 pin configurationadsst-218x ................................................ 10 general description of the adsst-73360lar adc ................ 11 specificationsadsst-73360lar ............................................. 12 absolute maximum ratingsadsst-73360lar .................... 14 esd caution ................................................................................ 14 pin configuration and pin function descriptions adsst-73360lar .......................................................................... 15 pin function descriptions ........................................................ 15 grounding and layout .............................................................. 16 power-up initialization and data from the adsst-salem-3t .................................................................... 17 voltage and current sensing .................................................... 17 accuracy of reference design using the adsst-salem-3t chipset ..................................................... 18 outline dimensions ....................................................................... 20 ordering guide ............................................................................... 21 revision history 7/04revision 0: initial version
adsst-salem-3t r e v. 0 | pa ge 3 o f 2 4 easy calib r ation the a d sst - s a lem-3t ch i p s e t has hig h ly ad v a n c e d ca lib r a t ion r o u t in es e m b e d d e d i n t o t h e s o f t wa r e . e a s e o f c a li b r a t ion is t h e k e y fe a t ur e i n t h is chi p s e t. by s e n d in g sp e c if ic c o mman d s t o t h e adsst - salem - 3t ch i p s e t, t h e dc o f fs ets a nd ga in s fo r a l l vol t - a g e and c u r r en t cha n n e ls can b e ca lib r a t e d a u toma t i c a l l y . a c t i ve a nd r e ac t i v e p o w e r ca lib r a t ion is a l s o a v a i lab l e fo r f i n e -t u n in g t h e er r o rs. the m e ter and ca lib r a t ion co nst a n t s a r e sto r e d in an ex ter n a l f l as h m e m o r y , a nd t h e lo ck/u nlo c k cal i b r a t ion fe a t ur e enab les prote c t i on of t h e c a l i br at i o n c o nst a n t s . t h e a b i l it y to up g r a d e t h e f i r m wa r e r e sidin g i n t h e f l as h m e m o r y mak e s t h e m e t e r a d a p t a bl e to f u tu re ne e d s . effective phase compensation t h e a d ss t - sal e m - 3 t c h i p set e m p l o y s a n al g o ri th m (pa t en t p e ndi n g ) fo r phas e com p en s a t i o n . th e a d sst - salem- 3t chi p s e t b a s e d m e ter , w h ich i s ver y ef fe c t i v e a nd us er f r ien d ly , ca n b e calib r a t e d fo r phas e co m p en s a t i o n a t t h re e c u r r en t p o in ts t o co v e r th e com p let e c u r r en t ra n g e . this als o r e d u ces t h e cos t o f t h e e nd p r o d uc t b y re d u cin g t h e cost o f t h e s e n s in g e l emen t s , i . e . , c u r r en t t r a n sfo r m e rs. ease of de sign d e sig n in g a com p let e m e t e r usin g t h e a d sst - salem-3 t is v e r y e a sy wi th t h e ads s t - sa l e m-3t -d k de ve lo p e r s ki t. th e ki t i n t h e u a r t m o de ena b les a us er t o e v al u a t e a nd t e st t h e co m p u t a t io nal elem e n t b y co nne c t i n g t o a p c , wi t h o u t b u i l ding t h e c o m p l e te h a rdw a re. quadra nt and other conventions t h e m e t e ri n g da ta co m p u t e d b y th e ad ss t - sa l e m- 3t c h i p se t us es t h e fol l o w in g co n v en t i on s fo r va r i o u s p a ra m e t e rs: ? f i gur e 2 gi v e s th e q u a d ra n t co n v en ti o n s use d b y th e chi p s e t. ? i m p o r t m e an s p o w e r de li v e r e d f r o m t h e u t ili t y to t h e us er . ? e x p o r t m e a n s p o w e r de li v e r e d b y t h e us er t o t h e u t ili t y . ? t o tal m e a n s t o t a l o f al l thr e e p h as es. i m p o r t and exp o r t a r e wi t h r e fer e n c e t o con s u m p t ion. u , i: m a g n i t u d e o f v o l t a g e and c u r r en t p : a c ti v e p o w e r (u i cos ) q: reac ti ve p o w e r (u i sin ) : p h as e an g l e f r o m t h e s t and p o i n t o f i w i t h r e sp e c t t o u , a l wa ys p o si t i ve i n co un t e r c lo ckwis e dir e c t ion. phas e u: l 1 = 0 a b s l2 = 240 a b s l3 = 120 a b s quadrant ii quadrant i p?q ? p+q? active export reactive export reactive import l1, l2, l3 active import reactive sin =? 1 reactive sin =+ 1 ( ? 90 ) (90 abs) (0 ) (0 abs) (+90 ) (270 abs) (180 ) (180 abs) active cos = +1 active cos =? 1 active capacitive (lead) active inductive (lag) quadrant iii quadrant iv p?q+ i q i p+q+ 037 38- 0- 00 2 f i g u re 2. q u adr a nt convent i ons
adsst-salem-3t rev. 0 | page 4 of 2 4 general description of the adsst-218x dsp the adss t - 21 8x is a sin g le-c hi p micr o c om p u ter o p timize d f o r dig i t a l sig n a l p r o c essin g (dsp) a nd o t h e r hig h sp e e d n u m e r i c p r o c e s s i n g ap p l i c at i o n s . the ds p com b in es t h e ads p -2 100 fa mil y bas e a r c h i t ec t u r e (t hr e e co m p u t a t io na l uni t s, d a t a addr ess ge n e r a to rs, a n d a p r o - g r a m s e q u en cer ) wi t h tw o s e r i al p o r t s, a 16-b i t in t e r n al d m a p o r t , a b y t e d m a p o r t , a p r og ra mma b l e timer , f l a g i/o , ext e n- si ve in ter r u p t ca p a b i li t i es, and on-ch i p p r o g r a m a nd da t a me mor y . the a d sst - 21 8x is fa b r ica t e d in a h i g h sp e e d , lo w p o w e r cmos p r o c es s. e v er y in s t r u c t io n can exe c u t e i n a sin g le p r o c - es s o r c y cle . the a d sst - 21 8x s f l exi b le a r chi t e c t u r e and com p r e h e n s i v e in st r u c t io n s e t e n a b le t h e p r o c e s s o r t o p e r f o r m m u l t i p le op era - tio n s in p a ral l e l . i n on e p r o c ess o r c y c l e , th e adss t - 218x can: ? gen e ra te th e n e xt p r ogra m ad dr es s ? fe t c h t h e n e x t i n s t r u c t i o n ? p e r f or m one or t w o d a t a move s ? u p da te on e o r t w o da t a a ddr ess p o in ters ? p e r f or m a c o m p ut a t i o n a l op e r at i o n this t a k e s pl ace w h ile t h e p r o c e s s o r co n t in ues to: ? r e cei v e a n d tra n sm i t da t a th r o ugh th e t w o se rial po r t s ? r e cei v e a n d / o r tra n sm i t da t a thr o ugh th e in t e rn al dm a p o r t ? r e cei v e a n d / o r tra n sm i t da t a thr o ugh th e b y t e d m a po r t ? decr e m en t t i m e r architecture overview the a d sst - 21 8x in st r u c t io n s e t p r o v ides f l exi b le d a t a m o v e s a nd m u l t if u n c t i o n (o ne o r tw o d a t a m o ves wi t h a com p u t a t ion) in st r u c t io n s . e v er y in st r u c t io n ca n b e exe c u t e d in a si n g le p r o c - es s o r c y c l e . th e adss t - 218x ass e m b l y la n g ua ge us es a n a l geb r a i c sy n t ax fo r e a s e o f co di n g an d r e a d ab i l i t y . a com p r e - he ns i v e s e t of d e vel opme n t to o l s supp or t s pro g r a m de velo pm en t. f i gur e 3 is th e f u n c tio n al b l o c k dia g ra m o f t h e adss t - 218x. the p r o c es s o r c o n t a i n s t h r e e indep e n d e n t com p u t a t ional uni t s : t h e al u , t h e m u l t i p lier/acc u m u l a t o r (ma c ), and t h e s h if t e r . the co m p u t a t iona l uni t s p r o c ess 16-b i t da t a dir e c t ly a n d h a ve prov i s i o ns to supp or t m u lt ipre c i s i on c o m p ut at i o ns . or me mo r y power-down control data address generators program sequencer arithmetic units serial ports data memory data timer full memory mode host mode external address bus external data bus external data bus internal dma port byte dma controller sport0 dag1 dag2 alu mac shifter adsp-2100 base architecture sport1 program memory address data memory address program memory data program memory 16k 24-bit data memory 16k 16-bit programmable i/o and flags 03 738 - 0 - 0 08 f i gur e 3 . f u nctio n al bl oc k dia g r a m
adsst-salem-3t r e v. 0 | pa ge 5 o f 2 4 e ffi c i e n t d a ta t r a n s f e r i s a c h i e v e d w i th t h e u s e o f fi v e i n t e r n a l bu s e s : ? p r ogra m m e m o r y a ddr es s (pma) b u s p r ogra m m e m o r y da t a (pmd) b u s ? da t a m e m o r y a ddr es s (d ma) b u s ? da t a m e m o r y da t a (d md ) bus ? res u l t (r) b u s t h e b y te me mo r y and i / o me mor y sp a c e i n te r f a c e supp or t s sl ow me mor i e s an d i / o me m o r y - m a p p e d p e r i p h e r a l s w i t h pro - g r a mma b l e wai t s t a t e g e n e ra t i on. e x t e r n al de vi ces ca n gain co n t r o l o f ext e rnal b u s e s wi t h b u s r e q u es t/g r a n t sig n als ( br , bg h , a n d bg 0 ). on e ex e c u t io n m o de (g o m o de) ena b les th e adss t - 218x t o co n t in ue r u nnin g f r o m o n -c hi p m e m o r y . n o r - mal exe c u t io n m o de r e q u ir es t h e p r o c e s s o r t o hal t w h i l e b u s e s are g r an te d. the a d sst - 21 8x ca n r e s p ond t o 11 in t e r r u p ts. ther e a r e u p t o s i x e x te r n a l i n te r r upt s ( o ne e d g e s e ns i t ive, t w o l e vel s e ns i t ive, a nd t h r e e co nf i g ur a b le) a nd s e ven i n ter n a l i n ter r u p ts gen e r a te d b y th e tim e r , th e se ri al po r t s (s po r t s), th e b y t e d m a po r t , a n d t h e p o w e r - do w n cir c ui t r y . th ere is als o a mas t e r res e t sig n al . t h e t w o s e r i a l p o r t s prov i d e a c o m p l e te s y n c h r onou s s e r i a l in ter f ace w i t h op t i o n a l co m p andin g i n ha r d wa re a nd a wi de va r i ety o f f r a m e d o r f r a m eless d a t a t r an smi t and r e cei v e m o des of op e r a t i o n . serial ports the adss t - 21 8x in co r p o r a t es tw o co m p lete sy n c hr on o u s s e r i a l p o r t s (s por t 0 a nd s p or t1) fo r s e r i a l co mm unica t io n s and m u l t i p r o ces s o r co mm unic a t io n. pac kag e des c ription the adss t - 21 8x is a v a i lab l e in a 100-lead lo w p r o f ile q u ad f l a t p a ck age ( l q f p , re f e r to f i g u re 5) .
adsst-salem-3t rev. 0 | page 6 of 24 adsst-218x common-mode pins table 2. pin name no. of pins i/o function bg 1 o bus grant output bgh 1 o bus grant hung output bms 1 o byte memory select output br 1 i bus request input cms 1 o combined memory select output dms 1 o data memory select output ioms 1 o memory select output pms 1 o program memory select output rd 1 o memory read enable output reset 1 i processor reset input wr 1 o memory write enable output irq2 / 1 i edge- or level-sensitive interrupt request 1 pf7 i/o programmable i/o pin irql1 / 1 i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irql0 / 1 i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irqe / 1 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode a 1 i mode select input?checked only during reset pf0 i/o programmable i/o pin during normal operation mode b 1 i mode select input?checked only during reset pf1 i/o programmable i/o pin during normal operation mode c 1 i mode select input?checked only during reset pf2 i/o programmable i/o pin during normal operation mode d 1 i mode select input?checked only during reset pf3 i/o programmable i/o pin during normal operation clkin, xtal 2 i clock or quartz crystal input clkout 1 o processor clock output ez-port 9 i/o for emulation use fi, fo flag in, flag out 2 fl0, fl1, fl2 3 o output flags gnd 10 i power and ground irq1 :0 edge- or level-sensitive interrupts pwd 1 i power-down control input sport0 5 i/o serial port i/o pins sport1 5 i/o serial port i/o pins pwdack 1 o power-down control output v ddext 4 i external v dd (2.5 v or 3.3 v) power (lqfp) v ddext 7 i external v dd (2.5 v or 3.3 v) power (mini-bga) v ddint 2 i internal v dd (2.5 v) power (lqfp) v ddint 4 i internal v dd (2.5 v) power (mini-bga) 1 interrupt/flag pins retain both functions co ncurrently. if imask is set to enable the corresponding interrup ts, the dsp will ve ctor to the appropriate interrupt vector address when the pin is asserted, either by ex ternal devices or set as a programmable flag. 2 sport configuration determined by the dsp system control regi ster. software configurable.
adsst-salem-3t r e v. 0 | pa ge 7 o f 2 4 clock sig n als ei t h er a cr y s t a l o r a t t l com p a t i b le clo c k sig n a l ca n clo c k t h e adss t - 218x. i f a n ext e r n al c l o c k is us ed , i t sho u ld be a t t l c o m p a t i b le sig n a l r u nnin g a t h a l f t h e i n st r u c t io n r a te. t h e sig n a l is co nne c t e d to t h e p r o c e s s o r s clki n in p u t. w h en an ext e r n al clo c k is us e d , th e x t a l i n p u t m u s t be le ft un co n n e ct e d . b e ca us e the adss t - 218x in c l u d es a n on-c hi p os cil l a t o r cir c ui t, a n ext e r n al cr ys tal m a y be use d . t h e cr ys tal s h o u ld be co nne c t e d acr o ss t h e c l ki n and xt al pin s , wi t h tw o ca p a c i t o rs co nnec t e d as sh o w n in f i gur e 4. th e ca p a ci t o r val u es a r e dep e n d e n t on t h e cr y s t a l ty p e a nd sh o u ld b e sp e c if ie d b y t h e c r y s t a l m a nu f a c t u r e r . a p a r a l l e l r e s o n a nt , f u n d a m e nt a l f r eq uen c y , micr o p r o ces s o r g r ade cr ys tal s h o u ld be us e d . a c l o c k o u t p u t (clk o u t) sig n al is g e n e r a t e d b y th e p r o c es s o r a t t h e p r o c ess o r s c y cle r a te. thi s ca n b e e n a b le d an d dis a b l e d b y t h e c l k o d i s b i t i n t h e s p o r t0 a u t o b u f f er co n t r o l r e g i s t er . clkin xtal dsp clkout 037 38- 0- 00 3 f i gure 4. ex te rn al c r ystal c o nnec t ions reset the res e t sig n al ini t ia t e s a mast er r e s e t o f th e ads s t - 2185x. the res e t sig n al m u s t be as s e r t e d d u r i n g th e p o w e r - u p s e qu e n c e to a s s u re prop e r i n it i a l i z a t i on . res e t d u r i ng ini t ia l p o w e r - u p m u s t be h e l d lo n g eno u g h t o ena b le t h e in t e r n al c l o c k t o s t a b iliz e . i f res e t i s a c ti v a t e d a n y tim e a f t e r po w e r - u p , th e clo c k co n t i n ues to r u n a nd do es n o t r e q u ir e st ab i l i z a t io n t i me. the p o w e r - u p s e q u ence is def i ne d as t h e to t a l t i m e r e q u ir e d fo r th e cr ys tal os cil l a t o r cir c ui t t o s t a b ilize a f t e r a va lid v dd is a p plie d t o t h e pr o c es s o r a nd fo r t h e i n t e r n al phas e-lo ck e d lo o p (p ll) t o lo c k on t o the s p ecif ic cr ys tal f r eq uen c y . a minim u m of 2000 clki n c y c l es en s u r e s tha t th e p ll has lo c k e d b u t do es n o t in cl ud e t h e cr ys tal oscilla t o r s t a r t - u p tim e . duri n g th i s po w e r - u p seq u en c e , th e res e t sig n al sh o u ld be he ld lo w . on an y su b s e q u e n t re s e t s , t h e res e t sig n al m u s t m e et t h e mini m u m p u ls e - wi d t h sp e c if ica t io n, t rs p . the res e t in p u t con t a i n s s o m e h y ste r esis; h o w e v e r , if a n rc cir c ui t is us ed to g e n e ra t e t h e res e t sig n al , t h e us e o f a n ext e r - na l s c hm i t t t r ig ger is r e co mm e n de d . recommended operat ing c o ndi t io ns table 3. p a r a m e t e r m i n m a x u n i t v ddin t 2 . 3 7 2 . 6 3 v v ddex t 2 . 3 7 3 . 6 0 v v inp u t 1 v il = C0.3 v ih = 3.6 v t amb 0 7 0 c 1 the adsst-2185x is 3.3 v tolerant (a lw ays accepts up to 3. 6 v max v ih ), but vol t age c o mpl iance (on output, v oh ) de pe nd s o n the input v ddext ; because v oh (m ax ) = v ddext ( max ). th i s a ppli e s t o bi di rect i o n a l pi n s (d 0Cd 23, r f s0, rfs1, sclk0, scl k 1, tfs0, a1Ca13, pf 0 Cpf7 ) a n d i n put on l y pi n s ( c lkin , re se t , br , dr0, dr1, pwd ).
adsst-salem-3t rev. 0 | page 8 of 24 adsst-218x electrical characteristics table 4. parameter test conditions min typ max unit v ih high level input voltage 1, 2 @ v ddint = max 1.5 v v ih high level clkin voltage @ v ddint = max 2.0 v v il low level input voltage 1, 3 @ v ddint = min 0.7 v v oh high level output voltage 1, 4, 5 @ v ddext = min, i oh = C0.5 ma 2.0 v @ v ddext = 3.0 v, i oh = C0.5 ma 2.4 v @ v ddext = min, i oh = C100 a 6 v ddext C 0.3 v v ol low level output voltage 1, 4, 5 @ v ddext = min, i ol = 2 ma 0.4 v i ih high level input current 3 @ v ddint = max, v in = 3.6 v 10 a i il low level input current 3 @ v ddint = max, v in = 0 v 10 a i ozh three-state leakage current 7 @ v ddext = max, v in = 3.6 v 8 10 a i ozl three-state leakage current 7 @ v ddext = max, v in = 0 v 8 10 a i dd supply current (idle) 9 @ v ddint = 2.5 v, t ck = 15 ns 9 ma @ v ddint = 2.5 v, t ck = 13.3 ns 10 ma i dd supply current (dynamic) 10 @ v ddint = 2.5 v, t ck = 13.3 ns 11 , t amb = +25c 35 ma @ v ddint = 2.5 v, t ck = 15 ns 11 , t amb = +25c 38 ma i dd supply current (power-down) 12 @ v ddint = 2.5 v, t amb = +25c in lowest power mode 100 ma c i input pin capacitance 3, 6 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25c 8 pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25c 8 pf 1 bidirectional pins: d0Cd23, rfs0, rfs1, sclk 0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2C0, bgh . 5 although specified for ttl outputs, all adsp-2186 outputs are cmos co mpatible and will drive to v ddext and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0Ca13, d0Cd23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0Cpf7. 8 0 v on br . 9 idle refers to adsst-218x state of operation during execution of idle instruction. deassert ed pins are driven to either v dd or gnd. 10 i dd measurement taken with all instructions exec uting from internal memory. 50% of the in structions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 11 v in = 0 v and 3 v. for typical figures for supply c urrents, refer to the powe r dissipation section. 12 applies to lqfp package type. 13 output pin capacitance is the capacitive load for any three-stated output pin.
adsst-salem-3t r e v. 0 | pa ge 9 o f 2 4 absolute maximum ratingsadsst-218x table 5. rating p a r a m e t e r m i n m a x internal supply voltage (v ddin t ) C0.3 v +3.0 v ex ternal supply voltage (v ddex t ) C0.3 v +4.0 v input voltage 1 C0.3 v +4.0 v output voltage swing 2 C0.5 v v ddex t + 0.5 v operating tem p erature range 0c 70c storage temperature range C65c +150c 1 appli e s t o bi di rect i o n a l pi ns (d0Cd23, rfs0, rfs1, scl k 0, sclk1, tfs0, tfs1, a1Ca13, pf0 Cpf7 ) a n d i n put - o n l y pi n s ( c lkin , re se t , br , dr0, dr1, pwd ). 2 a ppl ie s to o u tput pins ( bg , pms , dm s , bms , ioms , cms , rd , wr , p w d ack, a0, dt0, dt1, clko ut, fl2Cfl0, bgh ) . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . th es e a r e s t r e s s ra t i n g s o n l y ; f u n c t i o n al op era t i o n o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c - t i o n s o f t h is sp e c if ica t ion is n o t im plie d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. electrosta tic char ges as high as 4000 v readily ac cumulate on the human body and test eq uipment and c a n d i scharge wit h out d e tection. although th is product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
adsst-salem-3t rev. 0 | page 10 of 24 pin configurationadsst-218x 037 38- 0 - 0 0 9 5 4 3 2 7 6 9 8 1 d1 9 d1 8 d1 7 d1 6 ir qe + p f4 ir ql0 + p f 5 gn d ir ql1 + p f 6 dt0 tf s 0 sc l k 0 v d d ext dt1 / fo tf s 1 /i r q 1 dr 1/ f i gn d sc l k 1 er e set r eset d15 d14 d13 d12 gnd d11 d10 d9 v ddext gnd d8 d7/iwr d6/ird d5/ial d4/is gnd v ddint d3/iack d2/iad15 d1/iad14 d0/iad13 bg ebg br ebr a4/iad3 a5/iad4 a6/iad5 a7/iad6 a8/iad7 a9/iad8 a10/iad9 a 11/iad10 a 12/iad11 a 13/iad12 gnd gnd clkin xtal clkout gnd v ddint v ddext wr rd bms dms pms ioms cms 71 72 73 74 69 70 67 68 65 66 75 60 61 62 63 58 59 56 57 54 55 64 52 53 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pi n 1 i d e n ti fi e r t o p vi ew (n o t to s c a l e ) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 adsst-218x ir q2 + p f7 rfs 0 dr0 em s ee el o u t ec l k elin ei n t a3 /iad2 a2 /iad1 a1 /iad0 a0 p w dack bgh fl0 fl1 fl2 d2 3 d2 2 d2 1 d2 0 gnd pf 1 [m o d e b ] gnd pw d v d d ext pf 0 [ m o d e a ] pf 2 [m o d e c ] pf3 [ m od e d ] rf s 1 / i rq 0 f i gure 5. pin config ur ation f o r ad sst -218x in 100-l ead l qfp
adsst-salem-3t rev. 0 | page 11 of 24 general description of the adsst-73360la r adc the adss t - 73 360l ar is a 6-cha n n e l in p u t a n alog f r o n t en d p r o c es so r f o r g e n e ral-p u r p ose a p p l ica t io n s , in c l ud in g in d u s t r i al p o w e r m e t e r i n g o r m u l t ic ha nnel a n alog in p u ts. i t f e a t ur es six 16-b i t a/d con v ersio n c h a n n e ls, eac h o f which p r o v ides 76 db sig n a l -t o- n o is e ra t i o o v er a dc t o 4 kh z sig n a l b a ndwid t h . e a ch cha n n e l a l s o fe a t ur es a n i n p u t pr og ra mma b l e ga in am plif ier (pga) wi th ga in s e t t in gs in eig h t s t a g es f r o m 0 db t o 38 db . the adss t - 73 360l ar is p a r t ic u l a r l y s u i t a b le f o r in d u s t r i a l p o we r me te r i ng a s e a ch ch a n nel s a m p l e s s y nch r onou sly , e n su r - in g t h a t t h er e is n o (phas e ) de l a y b e twe e n t h e c o n v ersio n s. th e adss t - 73360 l a r als o f e a t ur es lo w g r o u p de la y co n v ersio n s on al l c h a n n e ls. an o n -chi p r e fe r e n c e v o l t a g e is in cl ude d w i t h a n o minal val u e o f 1.2 v . the adss t - 73 360l ar is a v ail a b l e in a 28-lead so i c p a c k a g e. vinp1 sdi sdifs sclk reset mclk se sdo sdofs vinn1 vinp2 vinn2 vinp3 vinn3 vinp4 refcap refout vinn4 vinp5 vinn5 vinp6 vinn6 signal conditioning reference decimator 0/38db pga 0/38db pga 0/38db pga 0/38db pga 0/38db pga 0/38db pga decimator decimator decimator decimator decimator signal conditioning signal conditioning signal conditioning signal conditioning signal conditioning signal - ? conditioning adsst-73360lar serial i/o port signal - ? conditioning signal - ? conditioning signal - ? conditioning signal - ? conditioning signal - ? conditioning 037 38- 0- 0 0 4 f i gur e 6 . adsst -7 33 60 lar f u nctio n al bl oc k dia g r a m
adsst-salem-3t rev. 0 | page 12 of 24 specificationsadsst-73360lar (avdd = 2.7 v to 3.6 v, dvdd = 2.7 v to 3.6 v, dgnd = agnd = 0 v, f mclk = 16.384 mhz, f sclk = 8.192 mhz, f s = 8 khz, t a = t min to t max 1 , unless otherwise noted.) table 6. parameter min typ max unit test conditions reference refcap absolute voltage, v refcap 1.08 1.2 1.32 v refcap tc 50 ppm/c 0.1 f capacitor required from refcap to agnd2 refout typical output impedance 130 ? absolute voltage, v refout 1.08 1.2 1.32 v unloaded minimum load resistance 1 k? maximum load capacitance 100 pf adc specifications maximum input range at vin 2, 3 1.578 v p-p measured differentially C2.85 dbm nominal reference level at vin (0 dbm0) 1.0954 v p-p measured differentially C6.02 dbm absolute gain pga = 0 db C1.3 +0.6 db 1.0 khz pga = 38 db C0.8 +0.8 db 1.0 khz signal to (noise + distortion) pga = 0 db 76 db 0 hz to 4 khz; f s = 8 khz pga = 0 db 71 76 db 0 hz to 2 khz; f s = 8 khz f in = 60 khz pga = 38 db 58 db 0 hz to 4 khz; f s = 64 khz total harmonic distortion pga = 0 db C80 C71 db 0 hz to 2 khz; f s = 8 khz; f in = 60 khz pga = 38 db C64 db 0 hz to 2 khz; f s = 64 khz; f in = 60 khz intermodulation distortion C78 db pga = 0 db idle channel noise C68 db pga = 0 db, f s = 64 khz; sclk = 16 mhz crosstalk adc-to-adc C95 db adc1 at idle; adc2 to adc6 input signal: 60 hz dc offset C30 +30 mv pga = 0 db power supply rejection C55 db input signal level at avdd and dvdd pins 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s 64 khz output sample rate 50 s 32 khz output sample rate 95 s 16 khz output sample rate 190 s 8 khz output sample rate input resistance at vin 2, 4 25 k? 6 dmclk = 16.384 mhz phase mismatch 0.15 degrees f in = 1 khz 0.01 degrees f in = 60 hz
adsst-salem-3t rev. 0 | page 13 of 24 parameter min typ max unit test conditions frequency response (adc) 7 typical output frequency (normalized to f s ) 0 0 db 0.03125 C0.1 db 0.0625 C0.25 db 0.125 C0.6 db 0.1875 C1.4 db 0.25 C2.8 db 0.3125 C4.5 db 0.375 C7.0 db 0.4375 C9.5 db > 0.5 < C12.5 db logic inputs v inh , input high voltage v dd C 0.8 v dd v v inl , input low voltage 0 0.8 v i ih , input current 10 a c in , input capacitance 10 pf logic output v oh , output high voltage v dd C 0.4 v dd v |i out | 100 a v ol , output low voltage 0 0.4 v |i out | 100 a three-state leakage current C10 +10 a power supplies avdd1, avdd2 2.7 3.6 v dvdd 2.7 3.6 v idd 8 see table 7 1 operating temperature range is as follows: C40c to +85c. therefore, t min = C40c and t max = +85c. 2 test conditions: input pga set for 0 db gain (unless otherwise noted). 3 at input to sigma-delta modulator of adc. 4 guaranteed by design. 5 overall group delay will be affected by the sa mple rate and the external digital filtering. 6 the adcs input impedance is inversely proportion al to dmclk and is approximated by: (4 10 11 )/dmclk. 7 frequency response of the adc measured with input at audio reference level (the input level that produces an output level of 0 dbm0), with 38 db preamplifier bypassed and input gain of 0 db. 8 test conditions: no load on digital inputs, analog inputs ac-coupled to ground. table 7. current summary (avdd = dvdd = 3.3 v) conditions digital current, max (ma) se mclk on comments adcs only on 25 1 yes refout disabled refcap only on 1.0 0 no refout disabled refcap and refout only on 3.5 0 no all sections on 26.5 1 yes refout enabled all sections off 1.0 1 yes mclk active levels equal to 0 v and dvdd all sections off 0.05 0 no digital inp uts static and equal to 0 v or dvdd the above values are in ma and are typical values, unless otherwise noted. mclk = 16.384 mhz; sclk = 16.384 mhz.
adsst-salem-3t rev. 0 | page 14 of 24 absolute maximum ratingsadsst-73360lar (t a = 25c un less o t h e r w is e no te d) table 8. p a r a m e t e r r a t i n g avdd, dvdd to gnd C0.3 v to +4.6 v agnd to dg nd C0.3 v to +0.3 v digital i/o voltage to dgnd C0.3 v to dv dd + 0.3 v analog i/o voltage to agnd C0.3 v to av dd operating temperature range 0c to +70c storage temperature range C65c to +150c maximum junction temperature 150c thermal imped a nce ja (soic) 75c/w s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . . esd caution esd (electrostatic discharge) sensitive device. electrosta tic char ges as high as 4000 v readily ac cumulate on the human body and test eq uipment and c a n d i scharge wit h out d e tection. although th is product features proprietary esd protection circ uitry, permanent dama ge may occur on devices subjected to high energy electrostatic di scharge s . ther efore, pro p er esd precautions are rec o m m ended to avoid performan c e degradation or l o ss of functiona l ity.
adsst-salem-3t rev. 0 | page 15 of 24 pin configuration an d pin function descri ptionsadsst-73360lar nc = no connect top view (not to scale) vinp2 1 vinn2 2 vinp1 3 vinn1 4 refout 5 refcap 6 avdd2 7 agnd2 8 dgnd 9 dvdd 10 reset 11 sclk 12 mclk 13 sdo 14 vinn3 vinp3 vinn4 vinp4 vinn5 28 24 27 26 25 vinp5 vinn6 vinp6 avdd1 20 23 22 21 agnd1 se sdi sdifs 16 19 18 17 sdofs 15 03 738- 0- 00 5 f i gure 7. adsst - 7 3360l a r pin config ur ationr w -28 pin func ti on descrip t io ns table 9. pin no. mnemonic function 1 vinp2 analog input to the positi ve terminal of input channe l 2. 2 vinn2 analog input to the nega tive te rminal of input channel 2. 3 vinp1 analog input to the positi ve terminal of input channe l 1. 4 vinn1 analog input to the negati ve te rminal of input channe l 1. 5 refout buffered output of th e internal reference, whic h has a no mina l value of 1.2 v. 6 r e f c a p reference voltage for adcs. a bypass capacitor to agnd2 of 0.1 f is required for the on-chi p reference. the c a pacitor should be fixed to this pin. the intern al reference can b e overdriven by an external reference connec ted to this pin if req u ired. 7 avdd2 analog power s u pply connection. 8 agnd2 analog ground/substrate connection. 9 dgnd digital ground/substrate connection. 10 dvdd digital power s u pply connecti o n. 11 reset active low reset signal. this in put resets the entire chip, rese tting the control re gisters and clearing the digital circuitry. 1 2 s c l k output serial clock whose rate determines the serial tran sfer rate to/ f rom the adsst- 73360lar. i t is used to clock dat a or control info rmation to and from the serial port (sport). the freq uency of sclk is eq ual to the freq ue ncy of the mas t er clock (mclk) divi ded by an integer number that is the product of the ex te r n al ma ster cloc k rate divider and the serial clock r a te divider. 13 mclk master clock input. mclk is dr i ven from an ext e rnal clock signal. 1 4 s d o serial data output of the ad sst- 73360lar. both data and control info rmation m a y be output on this pin a n d are cloc ked on the positive ed g e of sclk. sdo is in three-state when no information i s being transmi tted and when se is low. 1 5 s d o f s framing signal output for sdo serial transfer s. th e frame sync is one bit wide a n d it is active one sclk perio d before the first bit (msb) of each output word. sdofs is referenced to the positive edge of sclk. sdofs is in three-state when se is low. 1 6 s d i f s framing signal i n put for sdi seri al transfers. the frame sync is o n e bit wide and it is valid one sclk period before the first bit (msb) of each input word. sdifs is sampled on the negative edge of sclk and is ignored when se is low. 1 7 s d i serial data inpu t of the adss t-7 3360lar. both data and control information m a y be input on this pin and are clock e d on the negative edge of sclk. sdi is ign o red when se is low.
adsst-salem-3t rev. 0 | page 16 of 24 pin no. mnemonic function 1 8 s e sport enable. asynchronous input enable pin for the sport. when se is set low by the dsp, the output pins of the sport ar e three-stated an d the input pins are ignored. s c lk is also d i sabled interna lly in ord e r to d e crease p o wer d i ssip a tion. when se is brought high, the control a n d d a ta registers of the sport are at their origina l values (before se was br ought low); however, t h e timing counters and other in ternal registers are at their reset values. 19 agnd1 analog ground connectio n. 20 avdd1 analog power s u pply connection. 21 vinp6 analog input to the positi ve terminal of input channe l 6. 22 vinn6 analog input to the negati ve te rminal of input channe l 6. 23 vinp5 analog input to the positi ve terminal of input channe l 5. 24 vinn5 analog input to the negati ve te rminal of input channe l 5. 25 vinp4 analog input to the positi ve terminal of input channe l 4. 26 vinn4 analog input to the negati ve te rminal of input channe l 4. 27 vinp3 analog input to the positi ve terminal of input channe l 3. 28 vinn3 analog input to the negati ve te rminal of input channe l 3. grounding and layout s i n c e t h e a n alo g in p u ts t o the adss t - 73360 l a r a r e dif f er en t i a l , m o s t o f t h e v o l t a g e s in t h e a n alog m o d u l a t o r a r e co mm o n - m o d e v o l t a g es. th e e x ce l l en t co mm on- m o d e r e je c t io n o f t h e p a r t wi l l r e m o ve co mm o n - m o d e n o i s e o n t h es e in p u ts. th e a n al og a n d dig i tal su p p lies o f th e adss t - 73360 l a r a r e indep e nden t a nd s e p a r a tely p i n n e d o u t to m i nim i z e co u p li n g be tw e e n a n alog a n d di gi tal s e cti o n s o f th e dev i ce . th e dig i t a l f i l t ers o n t h e e n co der s e c t io n p r o v ide r e j e c t io n o f b r o a d b and n o is e o n t h e p o w e r s u p p lies, excep t a t i n teg e r m u l t i p les o f the m o d u l a t o r s a m p lin g f r e q uen c y . the dig i tal f i l t ers a l s o r e m o v e n o is e f r o m t h e ana l og in p u t s , p r o v ide d t h e so u r c e d o e s n o t sa t u ra t e t h e a n al og m o d u l a t o r . h o w e v e r , be ca us e t h e r e s o l u tio n o f the adss t - 73360 l a r s ad c is hig h a nd t h e n o is e l e v e l s f r o m th e adss t - 73360 l a r a r e s o lo w , ca r e m u st b e t a ke n w i t h re g a rd to g r ou nd i n g a n d l a y o ut . the p r in ted cir c ui t bo a r d tha t ho us es th e adss t - 73360 l a r sh o u ld b e desig n e d i n such a w a y t h a t t h e ana l o g a n d dig i t a l s e c t io n s a r e s e p a r a te d and co nf in e d to cer t a i n s e c t io n s o f t h e bo a r d . th e ads s t - 73360l ar p i n co nf igura t ion o f f e rs a ma jo r ad van t a g e i n t h a t i t s a n a l o g and dig i t a l i n ter f a c es a r e co n n e c te d o n o p p o si te sides o f th e p a c k a g e . this facil i ta t e s th e us e o f g r o u n d p l an es t h a t c a n be e a sily s e p a ra t e d , as sh o w n in f i gur e 8. analog ground digital ground 0 373 8- 0- 0 0 6 f i g u re 8. g r ou nd p l ane l a yout a minim u m et ch t e chniq u e is gen e ral l y b e s t fo r g r o u n d pl an es as i t g i ves t h e b e st shi e lding. dig i t a l and a n a l og g r o u n d pl an es s h o u ld b e jo in e d in onl y o n e p l ace . i f this co nnec tio n is c l os e to t h e d e vice, i t is r e co m m e n de d to us e a fer r i t e b e ad i n d u c t o r as shown i n f i g u re 9 . a v o i d r u nnin g dig i t a l li n e s u n d e r t h e d e vice fo r t h e y wi l l co u p l e n o is e on t o t h e die . th e a n alog g r o u n d pl an e sho u ld b e ena b le d t o r u n un der t h e ads s t - 73360 l a r t o a v o i d no is e co u p ling. the p o w e r s u p p l y lin e s t o t h e adss t - 73360 l a r s h o u l d us e as la rg e a t r ace as p o s s i b le t o p r o v ide lo w im p e dan c e p a t h s and r e d u ce t h e ef fe c t s o f g l i t ch es o n t h e p o w e r s u p p l y lin e s. f a s t swi t c h in g sig n al s s u c h as c l o c ks s h o u ld b e s h ie lde d wi t h dig i tal g r ou nd to a v oi d r a d i a t i n g noi s e to ot he r s e c t i o n s of t h e b o ard, a nd clo c k sig n a l s sh o u ld ne ver b e r u n n e a r t h e a n a l o g in p u t s . t r aces o n op p o si t e sides o f the bo a r d sh o u ld r u n a t r i g h t a n g l es to e a ch ot he r . t h i s w i l l re d u c e t h e e f f e c t s of f e e d - t h r ou g h th r o ugh th e boa r d . a m i cr os tri p t e c h n i q u e i s b y fa r th e be s t b u t is n o t a l wa y s p o ssi b le w i t h a doub le-sid e d b o a r d . i n t h is t e ch- niq u e, t h e co m p o n e n t side o f t h e b o a r d is d e di c a te d to g r o u nd plan es w h i l e sig n als a r e place d o n t h e o t her side . g o o d d e co u p li n g is im p o r t a n t w h en usin g h i g h sp e e d d e vices. al l a n alog a nd dig i t a l s u p p lies s h o u ld b e de cou p le d t o a g nd a nd d g nd , r e sp ec ti v e l y , wi t h 0 . 1 f cera mic ca p a ci t o rs in p a ral l e l wi t h 10 f ta n t al u m c a p a ci t o rs. t o ac hiev e t h e best f r o m th es e decou p lin g c a p a ci t o rs, th ey sh o u ld b e p l ace d as c l os e as p o ssib le t o t h e de vic e , ide a l l y r i g h t u p a g a i n s t i t . i n sy st ems wh e r e a co mm o n s u p p l y v o l t a g e i s used t o d r i v e bo th t h e a v d d and d v d d o f th e ads s t - 73360l ar , i t is re c o mme nde d t h a t t h e s y ste m s a v dd su p p ly b e u s e d . this su p p ly shou l d h a ve t h e re c o m m e n d e d ana l o g su p p ly de c o u p l i ng betw een t h e a v d d p i n s o f t h e adss t - 73360 l a r an d a g nd , a nd t h e r e co m m e n d e d dig i t a l su p p ly de co u p li n g ca p a c i to rs b e tw e e n t h e d v dd p i n an d d g nd .
adsst-salem-3t rev. 0 | page 17 of 24 power-up i n iti a lizati on a n d da ta fr om th e adsst-s alem-3t the a d sst - s a lem-3t -e v b o o t lo ads t h e co de f r o m t h e no n v o l a t i l e f l a s h me mor y a s sh ow n i n t h e bl o c k d i ag r a m of a f u n c t i ona l m e ter in f i gur e 1. the co nf igur a t i o n an d ca lib r a - ti o n d a ta also ge t s loa d ed f r o m th e n o n v o l a t ile m e m o r y . f o r f u r t h e r d e ta ils o n b o o t lo ad in g, r e f e r t o th e adss t - salem - 3t - d k (d e v e l o p er s k i t) u s er m a n u al . th e us er ma n u al als o des c r i bes v a r i o u s co mman d s fo r in s t an tan e o u s a nd com p u t e d pa r a m e t e r s . voltage and current sensing f i gur e 9 s h o w s t h e i n p u t s e c t ion fo r t h e v o l t a g e a nd c u r r en t s e c t io n s . b a s e d o n t h e v o l t a g e and c u r r en t val u es, t h e g u i s o f t wa r e i n t h e adsst - salem - 3t -d k com p u t es t h e va l u es o f r e sis t o r s r1, r2, a nd r3. th e clo s es t a v a i lab l e va l u es t o t h os e calc u l a t e d b y t h e gui s o f t wa r e s h o u ld b e s e le c t e d and us e d . r3 current input to adc channel neutral phase current r2 voltage input to adc channel neutral phase voltage r1 03 738 - 0 - 0 07 fi g u r e 9 . i n p u t s e c t i o n the adss t - 73 360l ar has a p e ak-t o - p e a k in p u t ra n g e o f v ref C (v ref 0.6525) t o v ref + (v ref 0.6525); f o r v ref = 2.5 v , this is 0.856 v t o 4.14 v p-p . this limi t def i n e s the r e sis t an ce n e tw o r k on t h e p o te n t i a l c i rc u i t s a n d t h e bu rd e n re s i st a n c e on t h e s e c - o nda r y side o f th e ct . s i nce t h e ads s t - 73360l ar is a uni p ol ar ad c, t h e ac p o ten t ia l an d c u r r en t sig n a l s ha ve to b e o f fs et b y s o me dc le vel. t h e r e fer e nce des i g n has a dc o f fs et o f 2.5 v . this l i m i t s th e peak -t o- peak s i gn al r a n g e o f po t e n t i a l a n d cu rr e n t t o 3.28 v p-p o r 1.16 v r m s. potential section the s e le c t ion o f t h e p o ten t ia l divider cir c ui t sho u ld b e such t h a t it c a n : ? ha n d l e h i g h s u r g e v o l t a g e s ? hav e m i n i mu m v a b u r d e n ? give a p pro x i m a t ely 1 v p e a k he adro om to ac c o mmo d a t e o v er v o l t a g es. cu rrent sectio n the s e l e c t ion of c t r a t i o and bu rde n re s i st anc e shou l d b e su c h th a t i t ca n : ? h a nd l e t h e c o m p l e te dy n a m i c r a nge for t h e c u r r e n t s i g n a l in p u t. ? give a p pro x i m a t ely 1 v p e a k he adro om to ac c o mmo d a t e lo ads wi t h hig h cr es t fac t o r s. the r e f e r e n c e desig n has a ct wi t h a t u r n s ra tio o f 1:2500 a n d b u r d en r e sis t ance o f 82 ? . this g e n e r a t e s 0.656 v r m s o r 0.928 v p e ak a t 20 a c u r r en t. this lea v es en o u g h ma rg in f o r c u r r en t p u ls es o r lo w cr es t fac t o r lo ads, s u ch as s m ps. th e maxim u m c u r r en t c a n be u p t o 32.768 a.
adsst-salem-3t rev. 0 | page 18 of 24 accuracy of reference design using the adsst-salem-3t chipset overall accuracy, power, and energy measurement the accuracy figures are measured under typical specified conditions, unless otherwise indicated. table 10. test conditions for reference design using a metal ct of class 0.5 accuracy parameter nominal value nominal voltage (phase to neutral) v n v n = 230 v 1% maximum voltage (phase to neutral) 300 v nominal current i n = 5 a maximum current i max i max = 20 a frequency f n = 50 hz/60 hz 10% temperature 23 2c table 11. maximum error (power and energies) current voltage pf min typ max unit 0.01 i n i < 0.05 i n v n 1.0 0.1 0.2 % 0.05 i n i < i max v n 1.0 0.1 0.2 % 0.02 i n i< 0.1 i n v n 0.5 lagging 0.15 0.35 % 0.8 leading 0.15 0.35 % 0.05 i n i < i max v n 0.5 lagging 0.1 0.2 % 0.8 leading 0.1 0.2 % table 12. unbalanced load error current voltage pf min typ max unit 0.05 i n i i max v n 1.0 0.15 0.2 % 0.1 i n i i max v n 0.5 lagging 0.15 0.2 % table 13. voltage variation error voltage current pf min typ max unit v n 10% 0.05 i n i i max 1.0 0.05 0.1 % v n 10% 0.1 i n i i max 0.5 lagging 0.05 0.1 % table 14. frequency variation errors frequency current pf min typ max unit f n 10% 0.05 i n i i max 1.0 0.05 0.1 % f n 10% 0.1 i n i i max 0.5 lagging 0.05 0.1 % table 15. harmonic distortion error current current min typ max unit 10% of 3 rd harmonic 0.05 i n i i max 0.05 0.1 % table 16. reverse phase sequence error current voltage min typ max unit 0.1 i n v n 0.05 %
adsst-salem-3t rev. 0 | page 19 of 24 table 17. voltage unbalance error current voltage min typ max unit i n v n + 15% v 0.1 0.2 % table 18. starting current min typ max unit 0.07 0.1 % of i n
adsst-salem-3t rev. 0 | page 20 of 24 outline dimensions top view (pins down) 1 25 26 51 50 75 76 100 14.00 bsc sq 0.50 bsc 0.27 0.22 0.17 1.60 max 12 typ 0.75 0.60 0.45 view a 16.00 bsc sq 12.00 ref 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bed f i g u re 10. 1 00-l e a d l o w pr of i l e q u ad f l at p a ck ag e [l qfp] (st - 10 0) di me nsio ns sho w n i n mi ll im e t e r s controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.33 (0.0130) 0.20 (0.0079) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10 f i gure 11. 28-l ead standar d s m all o u tline p a ck age [s oi c ] w i de body (r w - 28) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s)
adsst-salem-3t rev. 0 | page 21 of 24 ordering guide part number 1 temperature range processors included package adsst-em-3040 0c to +70c adsst-2185mkst-300 st-100 adsst-73360lar rw-28 adsst-em-3041 ?25c to +85c adsst-2185mbst-266 st-100 adsst-73360lar rw-28 1 for developers kit, order adsst-salem-3t-dk.
adsst-salem-3t rev. 0 | page 22 of 24 notes
adsst-salem-3t rev. 0 | page 23 of 24 notes
adsst-salem-3t rev. 0 | page 24 of 24 notes ? 2004 a n alo g devic e s, inc. all rig h ts res e rve d . t r ade m arks a n d re g i s - tered trade m arks are the property of their respective owners . d03738C0C 7/04(0)

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